FPGA

NEORV32 soft-core CPU (RISC-V) - bootloader is not working

Multiplexing a pin for i2c signals and normal output signals

Top Level Module IceCube2

Xilinx ISE Design Summary Is Blank?

Xilinx SP605 evaluation board question on ISE support

Sorting out 'Unbuffered IO' warnings for Lattice ICE40 Ultralite devices

FPGA Benchmarking algorithms

FPGA IO - parallel termination resistors

need help to understand a .py script

TVS diodes in FPGA development boards

WTB cheap low-end evaluation board and cables

Introducing delay between outputs on Max II CPLD

Review of FlashLINK JTAG interface

Interfacing LVDS laptop screen with fpga

Lattice: Low power/High Performance targets?

WTB: PCI-X Altera fpga board

FPGA for DRAM based memory expansion

Opening Gowin VCD files in Questa sim

Structural design

SystemVerilog Combinational weighted priority selection routine.

SOLVED: Multi-tier LUT based round-robin arbiter, Modelsim=Ok, Quartus=1h compi

Reasonably priced FPGA dev board that has RF i/o?

Newbie looking for advice on small glue logic in CPLD/FPGA/...

Logic for WVALID and AWVALID in AXI Master

FMEA of a digital design

Altera FPGA - Arria II GX EP2AGX45DF25I5N

Request for altera/Quartus VGA example

FPGA Benchmarking

Reading a file in Verilog

input [7:0] data; in verilog. Serial or parallel?

simulation in gowin fpga designer

Ring Oscillator to determine delay

Vivado - pin location conflict. Bug?

Some thoughts on AXI pipe handshake protocol and timing closure

Need some video Lecture to understand OOPS with System verilog

How to start with FPGA? Replacement for STK673-010.

Exercise-focused FPGA learning resource?

Creating a simple testbench

New generateur DDS with Altera cyclone IV.

Error In Encoder (Verilog Code)