FPGA

DINI Group DNV7F2A

Using embedded I2C in Lattice MachXO2 as DS3231

Simultaneous read/write with Quartus-|| single clock FIFOs

Resources for learning the FPGA implementation process in detail

Implementing Verilog designs in real hardware

Newbie ModelSim question

Issue with implementing data processing in VHDL code

Question about shortest-path algorithm during synchronous circuit synthesis

[newbie] Doubt on verilog code

Multiplexing a pin for i2c signals and normal output signals

Does the transceiver link rate affect your modules?

how to work an instantiation template (verilog-Xilinx) into SV design?

Anyone has diagram for Cyclone IV demo board (link to image inside)?

Xilinx ISE Design Summary Is Blank?

Buying a Microsemi/Microchip Libero lisense

where to start?

OpenCores.org login

Nesting arrays

GW1N BSRAM access time confusion

FPGA based unknown circuit application

Two Frequency Dividers on a GAL16V8

About that Wishbone B4's "SEL_I" signal

del

Cheap and easy way of converting Altera HSMC to Xilinx FMC?

Failed reading data from DDR4

GAL/PAL manual programming ?

Found Xilinx XC9500/XL CPLDs Programming Algorithms from Xilinx

Getting Started with a Alinx AN108 and Cyclone 2 Board Help

Video Upscaling and Overscan

clocking scheme/CDC for half-band filter

Xilinx ML506 Virtex-5 compact flash contents

Terasic DE5-NET

Lattice CrossLink NX EVB Clocking w/higher speed clocks

Want to borrow a FPGA devboard? (in Chch, NZ).

clock gen on fpga simulates correctly but doesnt work in hardware.

FPGA Verilog Project - Saving values for future processing

Looking for docs for Pico E-102 board.

Schematic of the circuit for XILINX XCVU13P VIRTEX.

Nanoboard 3000

Pixel to byte