FPGA

XC9500XL : using a GCK pin as regular IO to match long transition time clock

Help on translate schematics to Verilog.

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Lattice has silently removed free iCEcube2 license and now charging $471

How to drive wheel on FPGA?

ATF1502 programming & 'wrong' id (fake?)

REQ: AVNET SPARTAN-6 LX9 Microboard Files

Xilinx ISE Microblaze tutorials or examples available?

Hyperram to MAX10 (with no DQS shift)

Analog video output with FPGA ?

USB BLASTER (FTDI245 vs ch552x) Quartus “No Hardware”

If Lattice iCE40UltraPlus has DDR primitives like ODDR in Xilinx?

Gowin Simulation

A FPGA Audio System in raspberrypi size and open source later.

PS PL Communication using AXI DMA and FreeRTOS on zynq arty z7-20

State machine design choice

Programming (non-JTAG) MAX7000 devices

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Reading the programming of PAL chips

3 bit Dff Counter Issue

OpenCores.org login

How to design UART peripherals IP?

FPGA Verilog Project - Saving values for future processing

SD card/SDIO 3.0 level translation solution

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Gowin Vs. Yosys

BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.

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Failed reading data from DDR4

Pruning bits in digital downconverter (DDC)

VHDL CODE QUESTION

Programming with Topjtag trought blacfin only

Is my petalinux image too big?

Xil_Out32 causes my program to crash?

FPGA Bluetooth/WiFi Project

Verilog best way to replicate if else logic inside always block? Macros?

Lattice FPGA programmer

Design cascaded sinc filters, how to?

DDR3L -> DDR3 compatibility

GateMate - An European FPGA

Detection of damaged pins of FPGA - CYCLONE V - 5CSEBA2U23I7SN

AMD/Xilinx announced Spartan UltraScale+ family

MIPI RX low frequency

Can Microchip Configurable Logic Block (CLB) match UART address?