FPGA

Can Microchip Configurable Logic Block (CLB) match UART address?

capture data from ADC with ISERDESE not working

Xilinx ISE Microblaze tutorials or examples available?

VUnit, UVVM, OSVVM: What are similarities and differences?

Lattice IP use with Modelsim

Loss of connectivity with Virtex 6 FPGA after successful programming

Notes on Gowin ALU Primitive Usage

OpenCores.org login

How to drive wheel on FPGA?

Open IP Example Design in Verilog?

A FPGA Audio System in raspberrypi size and open source later.

XC9500XL : using a GCK pin as regular IO to match long transition time clock

Lattice has silently removed free iCEcube2 license and now charging $471

Help on translate schematics to Verilog.

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ATF1502 programming & 'wrong' id (fake?)

REQ: AVNET SPARTAN-6 LX9 Microboard Files

Hyperram to MAX10 (with no DQS shift)

Analog video output with FPGA ?

USB BLASTER (FTDI245 vs ch552x) Quartus “No Hardware”

If Lattice iCE40UltraPlus has DDR primitives like ODDR in Xilinx?

Gowin Simulation

PS PL Communication using AXI DMA and FreeRTOS on zynq arty z7-20

State machine design choice

Programming (non-JTAG) MAX7000 devices

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Reading the programming of PAL chips

3 bit Dff Counter Issue

How to design UART peripherals IP?

FPGA Verilog Project - Saving values for future processing

SD card/SDIO 3.0 level translation solution

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Gowin Vs. Yosys

BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.

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Failed reading data from DDR4

Pruning bits in digital downconverter (DDC)

VHDL CODE QUESTION

Programming with Topjtag trought blacfin only

Is my petalinux image too big?

Xil_Out32 causes my program to crash?

FPGA Bluetooth/WiFi Project

Verilog best way to replicate if else logic inside always block? Macros?

Lattice FPGA programmer