Hi,
To be on the safe side I checked all serial protocols on my STB-3 again. SPI, UART, LIN and CAN work as explained in the user manual. It is really only the I2C signal that is going crazy.
Cheers, mathstudi
To cover all bases for I2C decode of STB-3, Martin, mathstudi, can you setup your scope to get the results you see and Save a State file (scope settings) and post it here please.
You will need to add a .txt file extension for the forum to accept it.
Then we can load that set up file into any scope to double check settings are as they should be.
TIA
Wouldn't it be easier if you did it with your setup ?
Wouldn't it be easier if you did it with your setup ?
Possibly however it won't reveal any incorrect settings you make.
Busy with another project ATM so later can upload a 2000X Plus or 1104X-E State file.
Unsure if you can use any State file in a 2000X HD, never tried.....something I should try but only have 1000X HD here and what's the worst that can happen that a Default can't fix. Then we have recovery files to fix any real problems.....
Think best we stick to the same model series for recalling State files.
Possibly however it won't reveal any incorrect settings you make.
Understand this, but..
What should you be able to do wrong there...
Look again at my video, the clock is absolutely stable, more stable than the flank trigger in defpoms video.
And if you press stop, the trigger is out of the game.
Then it decodes from memory and that doesn't work, at least not for me.
You can also post your settings as screenshots, there are not so many.
More than the thresholds for clock and data, as well as the trigger setting you could not make.
Wouldn't it be easier if you did it with your setup ?
Possibly however it won't reveal any incorrect settings you make.
Busy with another project ATM so later can upload a 2000X Plus or 1104X-E State Setup file.
Unsure if you can use any State Setup file in a 2000X HD, never tried.....something I should try but only have 1000X HD here and what's the worst that can happen that a Default can't fix. Then we have recovery files to fix any real problems.....
Think best we stick to the same model series for recalling State Setup files.
Edit: State files are for other instruments, not DSO's.
Attached is a SDS1104X-E Setup file for I2C decoding basic scope settings however not the actual Decode settings which need be checked/set to match and Threshold levels set correctly.
Set Decode = ON
I2C
CLK = Ch1 = 50% trigger
Data = Ch4
Use Save/Recall, Recall to load the below Setup file from USB
SetupI2C.1104X-E.xml is the file name so remove the .txt extension. (.xml extensions not supported on this forum)
Here is my setup for the SDS2354X Plus and the STB-3 I2C Serial Decode:
Once with holdoff trigger (2 ms).
"Start Holdoff On" "Acq Start" or "Last Trig Time". Both times the same results.
After that I copied the trigger settings in the Decode Menu to the trigger using Protocol Copy, also here the same results.
Here is my setup for the SDS2354X Plus and the STB-3 I2C Serial Decode with the SPL2016 Logic Probes.
"Start Holdoff On" "Acq Start" or "Last Trig Time". Both times the same results.
Setups from my 2504HD...
Serial trigger I²C with Restart (this is the rockstable one), I²C with Start (and 5ms/div), Edge falling, 2ms Holdoff.
Use Save/Recall, Recall to load the below Setup file from USB
SetupI2C.1104X-E.xml is the file name so remove the .txt extension. (.xml extensions not supported on this forum)
Test it now, same result as before, see pic...
STB-3 I
2C packet flaws reported to HQ.
Just for the case:
The board has an Altera Max 10 FPGA and a 10pin Jtag header.
What would I need to read/program this ?
Just for the case:
The board has an Altera Max 10 FPGA and a 10pin Jtag header.
What would I need to read/program this ?
Unknown yet however I have asked if a flash/FW is required to remedy.
So we wait.
Does this mean that it's possible to run the telnet service on the newer firmware (1.5.2R2)? I don't understand how downgrading, configuring telnetd, and then updating again to a newer release will preserve the capability. Or am I reading this all wrong?
I'm currently on V1.3.9R6, and I'm loath to update to the 1.5.2 releases, and loose telnet and siglent_device_startup.sh capability.
In reply to -
Just received a SDS2104X Plus with V1.5.2R1, with disabled telnet. If you need telnet, the downgrade to 1.3.9R12 worked.
For some reason the telnet password no longer works, even after the downgrade (root/siglent_sds1000x_e), however to get around it just use telnetd -l /bin/sh
in the siglent_device_startup.sh
file, then it won't ask for any login details.
Updated then to 1.5.2R2, all good
Does this mean that it's possible to run the telnet service on the newer firmware (1.5.2R2)?
No need to run a telnet session for
any tricks.
More study required.
I'm keen to keep my proper timezone, and maintain the clock with NTP as I do today. Thus, the desire for a startup script, or equivalent. Haven't seen anything like that for the newer firmware versions.
I'm keen to keep my proper timezone, and maintain the clock with NTP as I do today. Thus, the desire for a startup script, or equivalent. Haven't seen anything like that for the newer firmware versions.
You don't need any of that. As I said more study required.
All the later FW can be rolled back to earlier versions.
Checksum of the file, for comparing, read out with intel quartus prime light and usb blaster.
I ordered my USB Blaster today from AliExpress. As soon as I get the USB blaster I will share my checksum.
Just for the case:
The board has an Altera Max 10 FPGA and a 10pin Jtag header.
What would I need to read/program this ?
The file should be in the FW package, so you can get it from there.
Also, the FW upgrade script does the FPGA programming so you can also feed it with a different file.
Just for the case:
The board has an Altera Max 10 FPGA and a 10pin Jtag header.
What would I need to read/program this ?
The file should be in the FW package, so you can get it from there.
Also, the FW upgrade script does the FPGA programming so you can also feed it with a different file.
This is for STB-3 or which there is no official/public FW.
This is for STB-3 or which there is no official/public FW.
Ohhhh... oopss... didn't follow the whole thread flow.
But now you're trying to use the board to test also extraction/programming of FPGA contents?? That will make them increase the price!
But now you're trying to use the board to test also extraction/programming of FPGA contents??
No, there are some faulty STD-3 out there and it seems only Jtag can fix them....if Siglent will share the file with us.
Bug report / feature requests moved
here.