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It is rather confusing to use an OP with input offset. In all cases except for the 1 mV case - that just matched the OPs input offset, the integrator is in saturation and the simulation thus not giving the normal behavior with feedback.
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Removed the simulations with input DC offset. There is the one with DC=0V left.
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Due to the offset in the OPs model, the integrator still goes to saturation. By chance the 1 mV case did not saturate, even without the resistor. So the only good one was the 1 mV case. 0 V DC level and no OPs offset would be even better as it is less confusing.
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The simulation looks more feasible with, for example, 2xLT1022..
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Ok. I think I understand where that timing information sits. Being so close in design to a delta sigma means it could actually be treated as a delta sigma with a sampling rate of 50Khz. This should mean our quantisation noise is already shifted way out of band. And could be digitally filtered.
I am struggling to find any references that detail what happens when the feedback clock rate is not equal to the sampling rate. But it is a solid start on the math to descibe the noise high and low pass filters. -
When you look into the sigma delta ADC datasheets you may see a lot of pictures with clock vs. sampling rate..
Some math is here as well
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found that video already, have re watched it about 6 times to try and get every last part of it to stick around long enough to understand it, But does not make clear what happens when say, the feedback clock is 50KHz, but the sampling clock is 1Mhz, as it would be walking its pattern between feedback clocks, and how it would deal with the small reversal each pattern, it certainly captures more information about the crossings, which would be equivalent to a faster sample rate, but not sure if the modulation noise is being hidden by the sampling rate being at the same frequency
edit: his math is saying the integrator should appear as a ~4KHz low pass filter for the input, so in the same ballpark as what the simulation gave us, and certainly helps deal with input noise. -
There is some similarity to an sigma delta ADC, but there also is a significant difference. We don't care about the position of the zero crossings during run-up. The only thing that is used is the number of comparator readings (and thus reference settings) of one type (e.g. positive).
There may still be some help from the SD-ADC noise calculations, but the main part is different direction.
I think the more helpful part might be looking at the noise of chopper / AZ amplifiers. -
Yep was only planning for noise calcs. As it is effectivly the same circuit and being sampled the same way for the modulation (and possibly run down phase with different parameters) and i now have an idea where oversampled sampling but same modulation would live. Its equivilent to a delta sigma with a flash ADC instead of a comparator.
Then the adc sample. Well it already only has 45KHz of bandwidth so it really cuts things down.
Main takeaways are the input noise is filtered at 1-4KHz. The quantisation noise. (Uncertainty in your pattern sampling) is reduced by the delta sigma math. And technically reduces the rundown uncertainty aswell. But working out those numbers will take me some time.
We also have from the simulations that where run that the integrator output is quite the low pass filter. So we should not have to add in much of its noise. Leaving the slope and adc diff amp to be calculated the conventional way. As they will still be the primary noise sources if I am interpriting it correctly
Edit: i think I may have the output low pass wrong. As it tracks the input with gain it may not have a dominant pole at all. And instead would be based on the slope amp bandwidth) -
There is no 1-4 kHz low pass filter at the input. Quite some of IMO's early simulations run the integrator to saturation and thus don't work right. The added resistor to keep the integrator from running off, causes a low pass type action instead of the integrating action (low pass with extremely low corner frequency, e.g. in the µHz region).
I think the comparison to the sigma-delta ADC is more confusing than helping: for the normal ADC operation there is no oversampling. It is more like the classical dual slope ADC: integrate over a fixed interval (e.g. 20 ms) and than measure the charge.
The feedback from the references during run-up is not about quantization, but counting charge and keeping the integrator from saturating. For the noise, one should consider the currents from the references as part of the current going in - the switching pattern is quasi fixed for the small range noise is concerning. One can even do this for the rundown part.
So the noise can be divided in the 2 groups: noise effecting the charge going in and noise measuring the residual charge.
For longer integration (e.g. > some 1-10 ms) the main noise comes from the charge actually going in. The main noise source are the resistors and the slow part of the integrator.
Quantization noise comes from the µC internal ADC only, when measuring the final charge. However it is at a low level and not an important source anymore (for 20 ms integration). If needed one could even reduce it even further: e.g. with less asymmetry in the the refs. and thus more resolution form the slow slope part and more gain before the ADC.
In theory one could look at the run-up part data as a kind of 1 st order SD converter. However the resulting resolution is to low to be useful. It is not even useful as a helper, as it also includes the main errors from the normal ADC operation. So this part is not helping. The simple theory to the SD ADCs has another problem often ignored: it applies to the average noise, or the case with a significant external signal. With a DC signal, the quantization is no longer white noise and there are so called idle tones. So a SD ADC used for a quasi DC signal has additional complications. -
sorry if I sometimes seem to repeat myself, there is a bit of this that I am trying to get my head around, and lack good examples elsewhere of it, I was way off on that corner frequency and should have stuck with my old math, the hope with the delta sigma stuff was mainly for a second way to approach the problem, there is not many resources out there for 3 or more slope converters, but the internet is overflowing with really detailed breakdowns for delta-sigma, including the concept of modulation noise being moved out of the frequency range your measuring, which may be a way to reduce the effects of crosstalk and the switching, but your right, the math behind it, while extracting information, does not actually give a quick and computationally cheap way to reduce errors in the slope measurement. FPGA yes, Micro no.
Based on a limited gain of 1,000,000, I think we can represent it as a virtual resistor R2 on our integrator, with a value of 25Gohm, so in this circuit there should be a 0 gain cut off somewhere around 18KHz, "IF" this is the case, the math for the rest of the noise works out nicely (not yet counting power supply noise),
during run down I would expect about 200uV RMS @ 500KHz bandwidth noise for the comparator,
during residue measurement I would expect about 750uV RMS @ 45KHz bandwidth for the ADC, or almost 1 full LSB of the ADC when treated as Pk-Pk, but in reality the breif moment the ADC sampling cap is open cuts off most of the low frequency contributions making it far lower than this in practive.
The reference noise seems to be mostly from the input resistors, ending up about 2800nV @ 18KHz bandwidth per reference if my math is close to the mark,
And for Charge going in, assuming 1 reference, and the input, there is about 4000nV @ 18KHz bandwidth of noise, this is not yet counting the buffer, so a noise current of about 160pA, or a charge noise of about 3.2 pico-coulombs RMS, out of about 800 nano-coulombs for say a 1V signal, or about 1 part in 250,000, I wonder if this is why some designs went for a current source method for there references.
Edit: eventually I'm going to have to write up a nicer way of representing the sum of all these noise sources, as the bandwidth limited parts being summed with higher bandwidth parts is getting a little complex, and I now fully understand what you meant about R12 being most of the noise in the ADC,
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I have also not found much on theoretical papers on the noise of a multi-slope or just a dual slope converter. There is a little in the HP journal article about the 3458, but not much. After doing the noise calculation and looking back on the 3458 design some points look a little odd - so not sure they had a good theory on noise.
For the calculation of the noise the extra slow phase in the rundown is more like a side note. So good noise calculation for a dual slope ADC would also be a good start. So I had to make my own thoughts / calculations about the noise. It is only approximate, especially when it comes to 1/f noise and an effective frequency to use.
For the µC internal ADC noise and the slope amplifier, I also get about a noise level at around the quantization of the ADC. This is also supported by measurements (e.g. just reading the ADC a 2nd time).
For noise numbers it is common to have them relative to the input, not the output.
For the charge going into the integrator, the modulation is for most of the part not an important part. For most noise sources one can calculate without the modulation. So there is not 18 kHz BW, but more like the ADC input transfer function with a 50 Hz ENBW. It is only the switching related part (e.g. jitter and scattering in charge injection) where the modulation frequency really matters. Another part where the modulation matters is a small odd part of the reference noise, mixed back from some 50 kHz down to near DC.
My approximation is to assume an bandwidth of one over integration time (should be correct and is used for SD ADCs too). With the 20 ms signal and 20 ms zero cycle most of the amplitude would be at around 25 Hz and some at 75 Hz , 125 Hz and so on. However the contribution from the 75 Hz and up should be rather small, as there is a 1/f part from the Fourier components of the square wave (+-1 in software) and another 1/f from the integrator. So the 75 Hz part should be something like 1/9 the amplitude and thus 1/81 the noise power. For this reason I take an effective frequency of 25 Hz as an approximation, knowing that this slightly overestimates the 1/f noise. The data (e.g for the OPs) are usually not that accurate anyway. For the noise sources one can than use a Spice simulation (noise calculation) or calculate by hand. The noise sources are before integration and are thus directly comparable to the input. Ideally one would integrate over the sin(x)/x transfer function, somehow taking into account the lower frequency limit from input chopping (AZ mode).
Because of the sinx/x function it is mainly the low frequency noise (e.g. 50 Hz BW with an effective frequency of some 25 Hz) that matters here. This means for the relevant OPs (buffer and slow integrator it is the 25 Hz noise density that matters).
There are other noise source that are difficult to calculate up front: the jitter of the control signals and variations in charge injection (e.g. with supply, but also intrinsic to the switches). Jitter is also complicated as jitter often tends to be not just white noise, but often with a large 1/f part. The relevant frequency here is the modulation frequency.
The main reason for calculating the noise is in my few to see which parts / parameters are important and to help optimizing some parameters like the integration cap or choice of OPs.
I somewhere have spreadsheet to combine the known noise parts together, for my ADC and a few ADC from DMMs where I have plans and that can be handled with the same framework.
Using current sources instead of just resistors from a reference level helps a little with noise, but only a tiny amount. In the current sources the voltage over the current setting resistors tends to be smaller and this increases the noise - so if not done carefully the small advantage may be lost. I think the use of current sources is more like for INL reasons, as the current is not directly effected by the voltage at the integrator input. Still it depends on the settling of the current sources. The current sources also eliminate the switch resistance - however this also means there is no compensation with the switch resistance at the input. -
A good topic for a PhD thesis, indeed..
Btw, in those "universal opamp models" in the simulation file above/below you may define the current and voltage noise density levels (currently zero) and corner freqs such you may do the noise analysis then.
Fyi - the "Slew rate" is in V/s, therefore 10Meg is 10V/us
PS: an another source of noise may come from a switching "asymmetry" caused by MCU's instructions "jittery".. An LA hooked at the signals may help.
Also I've fixed
the input 1mV offset of the OPA1641 to 0mV and now the result with DC=0V looks better..
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If a PhD thesis was that easy to get by brute force math, I would happily take it
Working from the reference area back towards the ADC with frequency noise bins, the reference ends up filtered way more than I originally expected, at U9's input, it looks to be down to about 300nV RMS noise over a 100KHz bandwidth in big part to R22/C13 and some of its own roll off with C210. (this is working off the assumption of C13 to ground while I unwrap its actual characteristic)
Mainly now working out how to break apart the 2 op amp circuits to forward analyse these, the self converging parts are the hard bits, e.g. the bias point of U8's inputs,
edit: ignore the blue notes on noise for now, Still working through that part with the binning, and these will not match it
edit2: C13 through feedback action will end up servoing out most low frequency reference noise referenced to U9's input, but in turn will couple any noise from the -12.2V reference rail straight back into the reference input, which at that point will have all the resistors and op amp noise summed in, as the attenuation of the references noise is currently so low to the input, is there any issue with rebasing C13 back to signal ground, at present it is a stronger signal than R22 at only 1-2 Hz,
Edit3: caught my error in the gain calculation, had one term reverse, all ok with C26/C28 now
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The Idea of having C13 relative to the -13V and not to ground is to an even lower corner frequency. This would not effect single conversions, but only has an effect on the AZ cycle reading signal and zero. For the zero reading the reference noise would have less effect. So the idea is to average the reference to make better use of the ref. signal during the zero reading. Looking at this in the frequency domain this gives some 25 Hz range noise than can come back.
There is some effect on the higher frequency noise - a little more noise for the positive reference, but less for the negative.
Effectively using the -13 V level works like a capacitance multiplier (about x 3).
For the reference noise part there should be 2 important frequency ranges: one is the obvious low frequency part, like < 50 Hz. Actually more like < 5 Hz and some 20-30 Hz (or some 10-20 Hz if a 3 step cycle is used). The main purpose of C13 is to suppress the 25 Hz part a little (for noise, already some 10 dB attenuation is quite effective. So one might get away with a slightly smaller C13 cap.
The other (I think some DMM design overlooked this) is the higher frequency part around the modulation frequency and some subharmonic (e.g. 50 KHz +-25 Hz , 25 kHz+-25 Hz), that can be mixed back to near DC. So no real need to worry about large bandwidth, but still a little avoidable noise at much higher frequency. Here C26,C28 and C13 help to keep this noise low. The LM399 has quite some white noise part (some 100 nV/sqrt(Hz)). Without C13 the measured noise in deed goes up noticeable.
Edit: for the noise, one can not use local bandwidth and multiply the noise densitiy with local bandwidth. One kind of needs to calculate the transfer function from the noise sources to the output or alternatively to the equivalent input. Only than at the end one can look at the relevant frequency bands and use the BW. This is something where Spice can be quite some help, at least to check if one gets the transfer function right and does not overlook some filtering or signal path. The reference amplification with C13 from the output is quite complicated on it's own to do the math by hand. -
All good, it can stay at -12.2V for now, there will be a feedback loop that may cause issues, but that can be a later thought on how to mitigate it.
now just getting stuck with how to sum up the noise for U8 pin 2, as it is all a bit self referential, R201-2 Noise is summed with a gain of 2 into the 13.4V signal, which is then attenuated by the 47/2K2 divider, where it is summed with a gain of 2 to -12.2, where it returns to the same node via R201-3 and R201-4, this is a bit of a head scratcher. -
With C13 to the negative ref. The Part around U8 and U9 gets quite tricky. So I would just leave that to a spice simulation. The extra small shift is another complication - though with so little shift, it should not change the noise much.
There is another feedback path around U9+U8 through C13. However stability is not a problem if C26,C28 are there a in a reasonable range. The point is that C26*R4 and C28*(R6+R7) should be well slower than the OPs GBW, but faster than C13*R22. -
Well not sure how the spice simulation will differ, but I've ended up with a value of 63280nV RMS for the positive Reference, and 1080nV RMS for the negative reference at full bandwidth, at the op amp outputs (1MHz)
For your sub 50Hz bandwidth it would be 1080nV for the positive and 890nV for the Negative at the op amp outputs,
due to the arrangement, any coupled noise will always have a gain of greater than 1 on the output of the positive reference, however the integrator does a quite good job at knocking this down by the time its come back around, at 8.7KHz (refined math) for a single input, the AC gain of the integrator becomes 0.5, as the capacitors reactance is half of the input resistance, it never reaches 0, but under that point most of the contributions are heavily attenuated. e.g. at 50KHz, the AC gain is only 0.086, an input + a reference reduce the effective input resistance to half, so the low pass pole becomes double, about 17.4KHz, or a gain of 0.17 at 50KHz,
Downside is the low frequency noise gets boosted by a large amount, at 50Hz, there is a AC gain of about 60 on the integrator, but as we are starting with rather low noise this should be ok
As I begin to calculate the noise forward into the ADC, I expect the total amount of noise to be slightly higher than my blue notes, but it is much more heavily shaped towards lower frequencies, I wish the OP07 had its broadband noise graph another decade longer, as at present it is the dominant noise source for anything over 100Hz on U9, if you open up its bandwidth to calculate forward with binning over the entire range it becomes a real problem, (assuming a flat 10nV/rootHz), and ends up contributing far more high frequency noise,
edit: the attached images are the noise density at the output of the references, as the frequency goes up, it would currently converge towards a gain of 1 for the positive reference, so towards a value of 10, as the low pass elements mean the rest of the influences are attenuated out. better op amps here would only remove about 60% of the noise if we used an OP27, the negative reference would not even see a 1% change.
edit2: U8 is an inverting amplifier, so I had to correct the noise graphs, the negative reference ends up much lower noise. left wondering if a better design could be with 2 inverting amplifiers so both have essentially no high frequency noise due to the roll off towards 0 gain, this would reduce the total noise of the positive reference 98% over the full 1MHz bandwidth,
The goal is it would not just attenuate the internal noise, but any coupled or external noise as well
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As low a noise as you get out of the references, the integrator AC gain at low frequencies is the real killer, this is just the references contribution to the integrator output, I have not yet summed it in with the integrator op amp and resistor noise or input buffer noise yet.
at 50Hz BW, you can expect 50uV RMS for Ref- during rundown, 100uV RMS for Ref- during modulation, and 60/121uV for Ref+ during these times, During rundown you end up with 20% less noise over 1MHz, during modulation you end up with about 60% more. this is all with 25K input resistors,
The input resistors noise swamp out the reference noise, reducing the full bandwidth contribution of the positive references noise to just 11% more noise at the integrator for that reference.
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The relevant reference point for the noise is usually the input. For the calculation it may be easier to follow the signal to the output and than divide by the transfer function from the input. When taking it relative to the input, the low frequency gain of the integrator is not a problem - it is more that the gain going down with frequency is a big help against higher frequency noise. So for the part going through the integrator the relevant noise is the low frequency part.
The input resistors to the integrator can be one of the larger noise sources. It is not only the resistor at the input, but equally important the other 2 resistors together. These noise sources set a good mark so see if other noise sources are really that relevant. It is kind of a good sign if the resistors are the largest noise source - with 50 K resistors, the 3 resistors together give the noise of a 100 K resistor and thus some 40 nV/Sqrt(Hz). This is a very good noise level. The 3458 is supposed to be at some 80-150 nV/sqrt(Hz).
The other point of orientation is the noise of the reference - this can be a significant noise source, if the signal is near null.
For the reference amplification one has to be careful replacing the OP07 with an OP27: I did that the other way around, because of the relatively high current noise of the OP27. -
Yeah, flipping it to 2 inverting op amps would be a much better option than the OP27,was just investigating the contribution of each effect.
I am actually calculating both the input and output noise, in this case the input noise to the integrator just ends up the same shape as the reference outputs graph with a vector sum of 20.1nV/rootHz,
I prefer the output graphs as that is the noise I am trying to work out, and for the references really makes it clear how much of an influence each parameter changes, but I will agree the integrator one is not very useful right now without the other noise sources summed in, but it does show that essentially all the noise voltage will be very low in frequency,
the 3458's noise, where specifically and at what bandwidth is that measured, If it is the integrator input, I still have to sum in the noise from U2, U11, the resistors between, and the input buffers, this will raise it, equally I have yet to sum in the power supply noise, which may push this higher, still in the world of sums of squares, we have a good head start, if you can give me that bandwidth, I will work out how much we can sum in and remain under
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The noise of the 7V buffered signal, atleast to the buffers input is attached, it is barely anything, and will be completely swamped by the input resistor. this is in large part to them being nice enough to list the LM399's output impedance, without that it would have been a real pain to calculate. the drop at around 100KHz is when some pole inside the reference significantly begins increasing its output impedance.
the current noise from the OP07's for all of the resistors in the reference really don't contribute in any significant way, a few hundred femptoamp * 5000 or 10000 ohms is still only 0.95-1.8nV/rootHz, only 1.6% of the influence of the voltage noise. but yes running through the math would put the OP27 out of running from current noise (did not update that part when I was comparing to it), and actual better alternative would be OP227but flipping to inverting is still a more significant reduction,
The other big current noise issue point is the integrator inputs, when your measuring the ADC with all the inputs disconnected, the effective DC resistance of the integrator is near infinite, so the drift stops, but the influence of the current noise skyrockets, This is what I suspect C17 and C37's actual role are for, to cut that down to a reasonable level for mid frequencies
I would suspect from all this that the ferrites are only to deal with the crosstalk from the digital inputs of the mux, as nothing I have modeled so far would even begin to get into there attenuating range. -
Ok, Think I found the graphs your referencing for the 3458, 50Hz bandwidth, If that is referenced to the input of the integrator, all is well,
The white noise portion of the 2 references are 20.1nV/RootHz for the negative reference, and 22.5nV/RootHz
We will beat the 10V range by a mile, has a headroom of about 160nV/Hz, the 22K input resistors would consume most of that, but as that is compared to an 8.5 digit multimeter, so I'm not too worried. and would not be hard to knock that down even further, and still leaves headroom for the buffers. on the direct input mux channel there is just a silly amount of noise margin, I'm going though adding PSRR noise now, this will hurt some things, but I doubt it will even touch that margin
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Ok, PSRR really does hurt the current positive reference, it doesn't touch the margin, but it starts drastically increasing reference noise above 500Hz, in order to not be noticeable means ensuring the power supply noise to that op amp is below 40uV RMS
Edit: well crud, looks like I don't get a free lunch with inverting vs non inverting, means the negative reference gets a but noisier
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How is the multislope adc doing? Summerbreak or board already in production?
-branadic-