FPGA

VHDL - Why is my testbench signal "X" (= bus conflict)?

Looking for good 32 bit pseudo RNG in SystemVerilog.

Easy way to see number of registers along datapath in Vivado?

FPGA DSP filter to convert 16bit words to 10bit words at higher sample rate

LFSR toggle rate?

Xilinx ISE implementation stage issues

Simulating Gowin IP cores

FPGA prices WTF

FPGA for DRAM based memory expansion

Simulating ISE 14.7 in Modelsim

how to decrypt Xilinx IPCORE source code

Heavily configured FPGAs

SOLVED: Multi-tier LUT based round-robin arbiter, Modelsim=Ok, Quartus=1h compi

Newbie looking for advice on small glue logic in CPLD/FPGA/...

Low input frequency (1MHz) multiplication via PLL

HDL code for positive edge triggered J-K flip-flop with preset and clear

Port <i_Clk50MHz> has illegal connections.

Introducing delay between outputs on Max II CPLD

Some notes on building nextpnr on Mac

Alternative to system generator Xilinx Fpga

generate SPI in verilog

SystemVerilog Combinational weighted priority selection routine.

Capturing ADC Data using LVDS interface

2nm Chips

Anyone has diagram for Cyclone IV demo board (link to image inside)?

Overcoming BGA FPGA, perhaps...

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Vivado: inferred exception to break timing loop: 'set_false_path -through ...'

Video pass-through Xilinx based device, general thoughts/queries

Altera on board USB blaster

Looking for advice on PAL/GAL programmer

Image processing accelerator

First FPGA project. Looking for advice

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Does an SPI to AXI Lite interface exist?

Pin assignment in SoC

How to Test Dynamic Power of (PLLs, LUTs, DFFs...etc)?

tRAS definition for DDR memory

Pin like interruption on Altera FPGA

What FPGAs Are Still Available?

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FPGA internal logic analyzer

Dual port ram with different data widths