FPGA

Replacing a Color Prom on a Donkey Kong Jr Arcade with a GAL22v10

Which FPGA does Siglent SDG2000x has?

[FS EU] Altera FPGA Board etc

Is this how MIPI DSI FPGA Bridge implemented? Constructive Criticism needed

FPGA MIPI CSI-2 Receiver Image ISP, making USB C Camera Lattice Crosslink NX

Altera's "Active serial" - is it really a plain SPI ?

where did all the lower end FPGAs go ??

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Anyone use Altera Quartus II software and Cyclone II FPGA?

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GateMate - An European FPGA

USB data pins driven directly by Zynq pins

[SOLD] Xilinx FPGA - Spartan 3E Starter Kit (UK)

Quartus ALTFP_SQRT IP not working in simulation

Interfacing peripherals that run on different clocks.

Cyclone IV PLL not working correctly

REQ: AVNET SPARTAN-6 LX9 Microboard Files

FPGA EEVBlog segments / Xilinx buyer's remorse

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FPGA Beginner question...would an FPGA have enough gates to perform this?

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Reset - Sync, Async or None At All

Any Interesting Projects For Zynq

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Verilog automatic one-hot encoding for state names

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How to start with FPGA? Replacement for STK673-010.

Lattice XP2 daisy chain failed to program

Trouble shooting ZCU111 RFSoC board

timed state machines VHDL

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Xilinx Announces Vitis

State Diagram Application

Is This a Good Beginner FPGA?

How Many Blocks Do You Use When Designing a FSM?

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Xilinx's "Device Lookup" Service

Teaching FPGA from/to home ?

FPGA under $10 ?

Help required in Library of Zyn 7010 by xilinx SoC

XC9500XL : using a GCK pin as regular IO to match long transition time clock

Microcontroller simulation using Xilinx FPGA

JESD204B over fiber

Can anyone program a PLS153 or a 82S153 from a good part/

If Lattice iCE40UltraPlus has DDR primitives like ODDR in Xilinx?

Indexed pins in constraints file?

Intel\Altera EP53F8QI Short to GND Fault

Video pass-through Xilinx based device, general thoughts/queries