FPGA

MachXO2 FIFO_DC - are clocks really independent?

Industry going to SV for synth instead of verilog? NOT DISCUSSION ON WHIC BETTER

Making Altera/Intel onboard JTAG myself ?

Can anyone program a PLS153 or a 82S153 from a good part/

set_{input,output}_delay for external bus

Kintex XC7K325T for $45

Recording data and using it in a verilog testbench

LFSR toggle rate?

Tools and Design Flows for DSP Algorithm Implementation in Xilinx FPGAs

#Rant: Intel can't even host files correctly.

[SOLVED!] Vivado elaborate fails

n00b question about gaming project

In Verilog, is it possible to define XXX only if a parameter is set?

Visualize the PCIe communication protocol

Searching for Quartus 14.0 installer [solved]

XC7A100T How Many GTP?

Implementing old PAL/GAL into HDL

FPGA implementation with Xilinx chips

Falling back to earth...

SIPO shift reg circuit to verilog

Xilinx XC2064 Development Board

Basic Clock and PLL Question -- reading datasheets

SPI flash security register issue

PLL Variable Clock Phase Shift

Sipeed Spartan Edge Accelerator Board and HDMI output

What is this board with ten Virtex FPGAs on it?

TinyTapeout

iCE40 PLL filter_range parameter

inout with physical pins in Verilog

Gowin MiniStar Nano Limited Edition

Intel/Altera FPGA board with HSMC 1.8V

Help Please: (Virtual) JTAG Interface - data transmission

MAX 10 common supply voltage banks 1a and 1b for ADC use

Understanding Skid Buffer Mechanism

xilinx xc4000 - anyone worked on it?

VHDL SPI core

Odd connectivity/signal integrity issues with FMC VITA FPGA connector

JESD204B over fiber

knjn's FPGA-PCI: is it a good deal?

Microblaze vs Zynq vs Zynq ultrascale+ applications, examples?