FPGA

iCE40UP - how to select SPI Master config mode?

I need a small fpga with 2-4MB of RAM and nothing else

True Dual-Port memory verification

Lattice Crosslink-NX and Certus-NX FPGAs

Replacing a Color Prom on a Donkey Kong Jr Arcade with a GAL22v10

How CORDIC sin/cos in HDL works.

Xilinx: interface microblaze to hard IP

How to hack the EP1K30TC144-3N ?

Moving design between different variants

Xilinx FPGA Drive Strength Explanation

case statement written so output is low, but sim shows high pulse?

Any clue with this HDMI IC Chip is = "TC9138A" (QFN package)?

Books for Digital Logic Design

ATF15XX Dev DK2 example file PLDs etc

Flash devices for FGPA

Altera Quartus II ROM megafunction?

Sampled AT40K10-2DQU Now What?

Should a new EPM3064A be 'blank'?

Looking for Easy-ABEL v4.x documentation (PAL, GAL)

Tools for programming 16V8 GAL

Fractional-N frequency synthesis does not work on Mach XO2 FPGA

Lattice Diamond verbose synthesis engine errors

Gowin FPGAs: What is equivalent of "AXI Bus" (Xilinx) in Gowin's IP Cores

WinCUPL - need to create a 10ns delay

Cant find the latch in my state machine

FPGA development board with MIPI

Xilinx SliceM LUTs as distributed RAMs: read-first, write-first, or selectable?

Help Understanding Xilinx timing constraints

Terasic DE5-NET

Using Cyclone 3 chip on PCB

Xilinx SDK - preconfigure DDR with data?

Address decoder

Issues programming TinyFPGA AX2

FPGA DSP filter to convert 16bit words to 10bit words at higher sample rate

Quartus Simulation Error: Formal port ".." has OPEN or no actual associated with

FPGA based I/Q generator

[SOLVED] Cyclone III project on Windows 10 with Quartus V13

Automated tests with Xilinx ISIM on windows

How often do new series of FPGAs come out (xilinx)

Issue with implementing data processing in VHDL code