FPGA

New Zynq based SOM

Synchronizing intermittent clock sources

VHDL on CPLD vs. FPGA

Beginner reg question

Rant about the quality of embedded SW support from FPGA manfacturers

TANG Nano 9K - non working external Flash memory (P25Q32SH)

need help to understand a .py script

Hacking surplus Pano Logic thin clients

Don't know what adapter I need

VHDLWhiz Advanced Course Sign-up

Lattice UltraPlus timing constraint help..

Altera to Xilinx

How to solve this FPGA Problem from Embedded SoPC Design with Nios II Processor

LED Matrix Logic

Switch between two inouts

Lattice: Low power/High Performance targets?

Custom SDR + optical fiber

Zynq Ultrascale+ RFSoC data converter port help

Spartan-6 CCLK switching to 50 MHz -- why?!

Simulating BRAM with lattice/aldec tools

Measuring On-chip resistive termination (impedance adaptation)

Fast Arbiters for On-Chip Network Switches

Kria SOM Carrier with Dual FMC?

Zynq board throws "pl35x_nand_cmd_function timed out" error

SOLVED: Multi-tier LUT based round-robin arbiter, Modelsim=Ok, Quartus=1h compi

FPGAs using a wireless camera?

Looking For ViewDraw

Is it safe to swap these FPGAs?

Altera MAX 10 accessing lpddr2 sdram

Intel\Altera EP53F8QI Short to GND Fault

Looking for Enterpoint development board manuals

LDPC soft decoding - a breadcrumb trail for others.

Xilinx: interface microblaze to hard IP

I am looking for a Pearson who will design the board PCB for FPGA.

Gowin triple speed ethernet MAC. Trouble with tx data

IceStudio with Ice40 UltraPlus Breakout

PS DDR Init fails: 0x00FD080030 PHY GeneralStatus Register0 stucks at Deskew ERR

Verilog coding style guidance needed

Synthesis : Pan's Algorithm

Basic Clock and PLL Question -- reading datasheets