FPGA

lockup latch issue

48-bit unsigned integer to 32-bit IEEE-754 float for Xilinx 7-series (VHDL)

ICE40 Board Design review

Anyone that moved from VHDL to SystemVerilog, what advice do you have for others

PMOD I2S2 codec attenuation with Cyclone IV

WinCUPL - need to create a 10ns delay

S_AXI_AWREADY always red X in Vivado simulator

DDR sdc commands

How SDC definition affects synthesis result?

Intro using Xilinx Artix7 MIPI CSI IP

softcore: getting started

Openocd with DE-10 nano (usb blaster 2) [Solved]

What is this board with ten Virtex FPGAs on it?

FPGA Beginner question...would an FPGA have enough gates to perform this?

« 1 2  All »

How to create SPI slave in FPGA when SCLK frequency similar to FPGA system clock

« 1 2  All »

EBAZ4205 (Zynq-7000 based development board)

« 1 2 3  All »

Xilinx Ethernet Network Client 101

Cyclone IV GX EP4CGX22 LVDS pins

Incrementing a counter in Verilog

Numato Labs Mimas A7 Mini FPGA Development Board - your experiences?

Serializing: shift registers vs. multiplexers

Alternatives to always@(posedge clk, negedge clk)

« 1 2 3  All »

How to feed an int to a third party module which wants a parameter in "Quotes"?

Vivado - ports not connected in implemented design

VHDL Case Statement

« 1 2 3  All »

Memory mapped SPI Dual port Ram

Xilinx SliceM LUTs as distributed RAMs: read-first, write-first, or selectable?

Multiported RAMs [SOLVED]

What is wrong with my if-else statment in this VHDL code for a counter? [SOLVED]

Lattice ECP5: opinion?

« 1 2  All »

Vivado - pin location conflict. Bug?

Any suggestion for small FPGA or CPLD in non BGA/CSP/QFN housing

« 1 2  All »

Can't get ISE10.1 to recognize platform xilinx platform cable on Win10 etc.??

Memory caches and large block copy

FMC recommendations for beginner RF

How to eliminate a reset input

Draw Arc in Verilog

Xilinx SDK - library for regex?

Machx03 I2C programming

GVim HDL editor, need help...